Designing circuits, such as those implemented on field programmable gate arrays (FPGAs), can be a complex process. For example, a user of the FPGA can have aggressive timing requirements for a FPGA circuit design. Meeting timing requirement(s) is one of the most challenging problems that circuit designers face. A lot of time and resources may be spent trying to resolve timing violations in circuit designs. As the complexity of circuit designs increase, new techniques for physical optimization of circuit designs are becoming increasingly important from timing perspective. Automated computer-aided design (CAD) implementation tools help circuit designers; however, automated place and route electronic design automation (EDA) solutions may be unable to resolve timing issues in the circuit design. As a result, circuit designers have to spend a lot of manual effort and time trying to close timing.